The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 02, 2022

Filed:

Sep. 29, 2017
Applicant:

Intel Corporation, Santa Clara, CA (US);

Inventors:

David M. Durham, Beaverton, OR (US);

Ravi L. Sahita, Portland, OR (US);

Vedvyas Shanbhogue, Austin, TX (US);

Barry E. Huntley, Hillsboro, OR (US);

Baiju Patel, Portland, OR (US);

Gideon Gerzon, Zichron Yaakov, IL;

Ioannis T. Schoinas, Portland, OR (US);

Hormuzd M. Khosravi, Portland, OR (US);

Siddhartha Chhabra, Portland, OR (US);

Carlos V. Rozas, Portland, OR (US);

Assignee:

Intel Corporation, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 3/06 (2006.01); G06F 9/455 (2018.01); H04L 9/08 (2006.01); G06F 12/14 (2006.01); G06F 21/62 (2013.01); H04L 9/32 (2006.01); G06F 21/60 (2013.01); G06F 21/64 (2013.01);
U.S. Cl.
CPC ...
G06F 3/0623 (2013.01); G06F 3/064 (2013.01); G06F 3/0679 (2013.01); G06F 9/45558 (2013.01); G06F 12/1408 (2013.01); G06F 21/60 (2013.01); G06F 21/62 (2013.01); G06F 21/64 (2013.01); H04L 9/0897 (2013.01); H04L 9/3247 (2013.01);
Abstract

There is disclosed a microprocessor, including: a processing core; and a total memory encryption (TME) engine to provide TME for a first trust domain (TD), and further to: allocate a block of physical memory to the first TD and a first cryptographic key to the first TD; map within an extended page table (EPT) a host physical address (HPA) space to a guest physical address (GPA) space of the TD; create a memory ownership table (MOT) entry for a memory page within the block of physical memory, wherein the MOT table comprises a GPA reverse mapping; encrypt the MOT entry using the first cryptographic key; and append to the MOT entry verification data, wherein the MOT entry verification data enables detection of an attack on the MOT entry.


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