The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Aug. 02, 2022
Filed:
May. 11, 2020
Applied Materials, Inc., Santa Clara, CA (US);
Kurtis Leschkies, San Jose, CA (US);
Wei-Sheng Lei, San Jose, CA (US);
Jeffrey L. Franklin, Albuquerque, NM (US);
Jean Delmas, Santa Clara, CA (US);
Han-Wen Chen, Cupertino, CA (US);
Giback Park, San Jose, CA (US);
Steven Verhaverbeke, San Francisco, CA (US);
APPLIED MATERIALS, INC., Santa Clara, CA (US);
Abstract
A method of fabricating a frame to enclose one or more semiconductor dies includes forming one or more features including one or more cavities and one or more through-vias in a substrate by a first laser ablation process, filling the one or more through-vias with a dielectric material, and forming a via-in-via in the dielectric material filled in each of the one or more through-vias by a second laser ablation process. The one or more cavities is configured to enclose one or more semiconductor dies therein. In the first laser ablation process, frequency, pulse width, and pulse energy of a first pulsed laser beam to irradiate the substrate are tuned based on a depth of the one or more features. In the second laser ablation process, frequency, pulse width, and pulse energy of a second pulsed laser beam to irradiate the dielectric material are tuned based on a depth of the via-in-via.