The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 19, 2022

Filed:

May. 18, 2020
Applicant:

Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu, TW;

Inventors:

Tetsu Ohtou, Hsinchu, TW;

Ching-Wei Tsai, Hsinchu, TW;

Kuan-Lun Cheng, Hsinchu, TW;

Yasutoshi Okuno, Hsinchu, TW;

Jiun-Jia Huang, Yunlin County, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 27/11 (2006.01); H01L 27/088 (2006.01); H01L 29/10 (2006.01); H01L 21/8234 (2006.01); H01L 29/06 (2006.01); H01L 21/8238 (2006.01); H01L 27/092 (2006.01);
U.S. Cl.
CPC ...
H01L 27/1104 (2013.01); H01L 21/823418 (2013.01); H01L 21/823431 (2013.01); H01L 21/823468 (2013.01); H01L 21/823481 (2013.01); H01L 21/823807 (2013.01); H01L 21/823814 (2013.01); H01L 21/823821 (2013.01); H01L 21/823864 (2013.01); H01L 27/0886 (2013.01); H01L 27/0924 (2013.01); H01L 29/0649 (2013.01); H01L 29/1095 (2013.01); H01L 21/823878 (2013.01);
Abstract

A method includes forming a first semiconductor fin and a second semiconductor fin over a substrate; forming an shallow trench isolation (STI) structure on the substrate and between the first semiconductor fin and the second semiconductor fin; forming a spacer layer on the first semiconductor fin, the second semiconductor fin, and the STI structure; patterning the spacer layer to form a spacer extending along the second sidewall of the first semiconductor fin, a top surface of the STI structure, and the second sidewall of the second semiconductor fin; forming a first epitaxy structure in contact with a top surface of the first semiconductor fin and the first sidewall of the first semiconductor fin; and forming a second epitaxy structure in contact with a top surface of the second semiconductor fin and the first sidewall of the second semiconductor fin.


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