The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 19, 2022

Filed:

Dec. 18, 2019
Applicant:

Infineon Technologies Ag, Neubiberg, DE;

Inventors:

Stuart Cardwell, Crowborough, GB;

Chee Yang Ng, Muar Johor, MY;

Josef Maerz, Oberhaching, DE;

Clive O'Dell, Horley, GB;

Mark Pavier, Felbridge, GB;

Assignee:

Infineon Technologies AG, Neubiberg, DE;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/495 (2006.01); H01L 23/34 (2006.01); H01L 21/00 (2006.01); H01L 21/44 (2006.01); H05K 7/18 (2006.01); H01L 23/00 (2006.01); H01L 23/522 (2006.01); H01L 23/31 (2006.01);
U.S. Cl.
CPC ...
H01L 23/4952 (2013.01); H01L 23/3107 (2013.01); H01L 23/49503 (2013.01); H01L 23/49531 (2013.01); H01L 23/49551 (2013.01); H01L 23/49568 (2013.01); H01L 23/49575 (2013.01); H01L 23/5226 (2013.01); H01L 24/14 (2013.01); H01L 24/30 (2013.01); H01L 24/32 (2013.01); H01L 24/33 (2013.01);
Abstract

A semiconductor device includes a conductive frame comprising a die attach surface that is substantially planar, a semiconductor die comprising a first load on a rear surface and a second terminal disposed on a main surface, a first conductive contact structure disposed on the die attach surface, and a second conductive contact structure on the main surface. The first conductive contact structure vertically extends past a plane of the main surface of the semiconductor die. The first conductive contact structure is electrically isolated from the main surface of the semiconductor die by an electrical isolation structure. An upper surface of the electrical isolation structure is below the main surface of the semiconductor die.


Find Patent Forward Citations

Loading…