The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 19, 2022

Filed:

Sep. 12, 2019
Applicant:

Silicon Storage Technology, Inc., San Jose, CA (US);

Inventors:

Hieu Van Tran, San Jose, CA (US);

Thuan Vu, San Jose, CA (US);

Stephen Trinh, San Jose, CA (US);

Stanley Hong, San Jose, CA (US);

Anh Ly, San Jose, CA (US);

Steven Lemke, Boulder Creek, CA (US);

Nha Nguyen, San Jose, CA (US);

Vipin Tiwari, Dublin, CA (US);

Nhan Do, Saratoga, CA (US);

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 16/34 (2006.01); G11C 16/10 (2006.01); G06N 3/063 (2006.01); G06F 3/06 (2006.01); G06N 3/08 (2006.01); G11C 16/26 (2006.01); G11C 29/10 (2006.01);
U.S. Cl.
CPC ...
G11C 16/3459 (2013.01); G06F 3/0688 (2013.01); G06N 3/063 (2013.01); G06N 3/08 (2013.01); G11C 16/10 (2013.01); G11C 16/26 (2013.01); G11C 16/3436 (2013.01); G11C 29/10 (2013.01);
Abstract

Testing circuitry and methods are disclosed for use with analog neural memory in deep learning artificial neural networks. The analog neural memory comprises one or more arrays of non-volatile memory cells. The testing circuitry and methods can be utilized during sort tests, qualification tests, and other tests to verify programming operations of one or more cells.


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