The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 19, 2022

Filed:

Dec. 07, 2020
Applicant:

Micron Technology, Inc., Boise, ID (US);

Inventors:

Fei Xu, Shanghai, CN;

Dong Pan, Boise, ID (US);

Wei Lu Chu, Shanghai, CN;

Assignee:

Micron Technology, Inc., Boise, ID (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 7/14 (2006.01); G11C 7/10 (2006.01); G11C 16/34 (2006.01); G11C 16/30 (2006.01); G11C 5/14 (2006.01);
U.S. Cl.
CPC ...
G11C 7/14 (2013.01); G11C 5/14 (2013.01); G11C 5/147 (2013.01); G11C 7/1051 (2013.01); G11C 7/1078 (2013.01); G11C 16/30 (2013.01); G11C 16/34 (2013.01);
Abstract

Methods, systems, and devices for limiting regulator overshoot during power up are described. In some examples, a memory device may generate a first voltage at a first input node of an amplifier of a memory device based on an application, by an external supply, of a second voltage to a terminal of the memory device. The memory device may generate a third voltage at a second node of the amplifier at an amplifier at an offset to the first voltage, where the second node is coupled with a first gate of a first cascode transistor and a second gate of a second cascode transistor. The memory device may activate the amplifier based on generating the third voltage at the second node of the amplifier.


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