The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 19, 2022

Filed:

Sep. 25, 2019
Applicant:

Intel Corporation, Santa Clara, CA (US);

Inventors:

David Koufaty, Portland, OR (US);

Rajesh Sankaran, Portland, OR (US);

Anna Trikalinou, Hillsboro, OR (US);

Rupin Vakharwala, Hillsboro, OR (US);

Assignee:

Intel Corporation, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G06F 12/14 (2006.01); G06F 12/0862 (2016.01); G06F 12/1009 (2016.01); G06F 13/16 (2006.01); G06F 13/42 (2006.01);
U.S. Cl.
CPC ...
G06F 12/1483 (2013.01); G06F 12/0862 (2013.01); G06F 12/1009 (2013.01); G06F 13/1668 (2013.01); G06F 13/4282 (2013.01); G06F 2212/1052 (2013.01); G06F 2212/305 (2013.01); G06F 2212/6028 (2013.01); G06F 2213/0026 (2013.01);
Abstract

Embodiments are directed to providing a secure address translation service. An embodiment of a system includes DRAM for storage of data, an IOMMU coupled to the DRAM, and a host-to-device link to couple the IOMMU with one or more devices and to operate as a translation agent on behalf of one or more devices in connection with memory operations relating to the DRAM, including receiving a translated request from a discrete device via the host-to-device link specifying a memory operation and a physical address within the DRAM pertaining to the memory operation, determining page access permissions assigned to a context of the discrete device for a physical page of the DRAM within which the physical address resides, allowing the memory operation to proceed when the page access permissions permit the memory operation, and blocking the memory operation when the page access permissions do not permit the memory operation.


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