The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 19, 2022

Filed:

May. 22, 2020
Applicant:

Texas Instruments Incorporated, Dallas, TX (US);

Inventors:

Abhijeet Ashok Chachad, Plano, TX (US);

Timothy David Anderson, University City, TX (US);

Pramod Kumar Swami, Bangalore, IN;

Naveen Bhoria, Plano, TX (US);

David Matthew Thompson, Dallas, TX (US);

Neelima Muralidharan, Murphy, TX (US);

Assignee:
Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
G06F 12/08 (2016.01); G06F 12/0811 (2016.01); G06F 12/10 (2016.01);
U.S. Cl.
CPC ...
G06F 12/0811 (2013.01); G06F 12/10 (2013.01); G06F 2212/608 (2013.01);
Abstract

An apparatus includes first CPU and second CPU cores, a L1 cache subsystem coupled to the first CPU core and comprising a L1 controller, and a L2 cache subsystem coupled to the L1 cache subsystem and to the second CPU core. The L2 cache subsystem includes a L2 memory and a L2 controller configured to operate in an aliased mode in response to a value in a memory map control register being asserted. In the aliased mode, the L2 controller receives a first request from the first CPU core directed to a virtual address in the L2 memory, receives a second request from the second CPU core directed to the virtual address in the L2 memory, directs the first request to a physical address A in the L2 memory, and directs the second request to a physical address B in the L2 memory.


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