The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jul. 19, 2022
Filed:
Jun. 05, 2020
Intel Corporation, Santa Clara, CA (US);
Jawad Khan, Portland, OR (US);
Chetan Chauhan, Folsom, CA (US);
Rajesh Sundaram, Folsom, CA (US);
Sourabh Dongaonkar, Santa Clara, CA (US);
Sandeep Guliani, Folsom, CA (US);
Dipanjan Sengupta, Hillsboro, OR (US);
Mariano Tepper, Santa Clara, CA (US);
Intel Corporation, Santa Clara, CA (US);
Abstract
Technologies for column reads for clustered data include a device having a column-addressable memory and circuitry connected to the memory. The column-addressable memory includes multiple dies. The circuitry may be configured to determine multiple die offsets based on a logical column number of the data cluster, determine a base address based on the logical column number, program the dies with the die offsets. The circuitry is further to read logical column data from the column-addressable memory. To read the data, each die adds the corresponding die offset to the base address. The column-addressable memory may include multiple command/address buses. The circuitry may determine a starting address for each of multiple logical columns and issue a column read for each starting address via a corresponding command/address bus. Other embodiments are described and claimed.