The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 19, 2022

Filed:

Dec. 27, 2019
Applicant:

Intel Corporation, Santa Clara, CA (US);

Inventors:

Deepak Gupta, Portland, OR (US);

Mingwei Zhang, Hillsboro, OR (US);

Ravi Sahita, Portland, OR (US);

Vedvyas Shanbhogue, Austin, TX (US);

Michael Lemay, Hillsboro, OR (US);

David M. Durham, Hillsboro, OR (US);

Assignee:

INTEL CORPORATION, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 12/02 (2006.01); G06F 9/30 (2018.01); G06F 12/0895 (2016.01); G06F 12/1036 (2016.01); G06F 12/14 (2006.01); G06F 12/1009 (2016.01);
U.S. Cl.
CPC ...
G06F 12/0292 (2013.01); G06F 9/30101 (2013.01); G06F 12/0246 (2013.01); G06F 12/0895 (2013.01); G06F 2212/7201 (2013.01); G06F 2212/7207 (2013.01); G06F 2212/7209 (2013.01);
Abstract

An apparatus and method for memory management using compartmentalization. For example, one embodiment of a processor comprises: execution circuitry to execute instructions and process data, at least one instruction to generate a system memory access request using a first linear address; and address translation circuitry to perform a first walk operation through a set of one or more address translation tables to translate the first linear address to a first physical address, the address translation circuitry to concurrently perform a second walk operation through a set of one or more linear address metadata tables to identify metadata associated with the linear address, and to use one or more portions of the metadata to validate access by the at least one instruction to the first physical address.


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