The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 19, 2022

Filed:

Jun. 27, 2018
Applicant:

Intel Corporation, Santa Clara, CA (US);

Inventors:

Amin Firoozshahian, Mountain View, CA (US);

Omid Azizi, Redwood City, CA (US);

Chandan Egbert, San Jose, CA (US);

David Hansen, Santa Clara, CA (US);

Andreas Kleen, Portland, OR (US);

Mahesh Maddury, Santa Clara, CA (US);

Mahesh Madhav, Portland, OR (US);

Alexandre Solomatnikov, San Carlos, CA (US);

John Peter Stevenson, Chicago, IL (US);

Assignee:

Intel Corporation, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G06F 12/02 (2006.01); G06F 3/06 (2006.01); G06F 12/1009 (2016.01);
U.S. Cl.
CPC ...
G06F 12/0261 (2013.01); G06F 3/0608 (2013.01); G06F 3/0641 (2013.01); G06F 3/0679 (2013.01); G06F 12/0246 (2013.01); G06F 12/1009 (2013.01); G06F 2212/401 (2013.01); G06F 2212/7201 (2013.01); G06F 2212/7205 (2013.01);
Abstract

Processing circuitry for computer memory management includes memory reduction circuitry to implement a memory reduction technique; and reference count information collection circuitry to: access a memory region, the memory region subject to the memory reduction technique; obtain an indication of memory reduction of the memory region; calculate metrics based on the indication of memory reduction of cache lines associated with the memory region; and provide the metrics to a system software component for use in memory management mechanisms.


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