The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 12, 2022

Filed:

Sep. 13, 2018
Applicant:

Intel Corporation, Santa Clara, CA (US);

Inventors:

Huichu Liu, Santa Clara, CA (US);

Tanay Karnik, Portland, OR (US);

Sasikanth Manipatruni, Portland, OR (US);

Daniel Morris, Hillsboro, OR (US);

Kaushik Vaidyanathan, Santa Clara, CA (US);

Ian Young, Portland, OR (US);

Assignee:

Intel Corporation, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 11/00 (2006.01); H01L 43/02 (2006.01); H01L 43/10 (2006.01); H01L 43/06 (2006.01); G11C 11/16 (2006.01); G11C 11/18 (2006.01);
U.S. Cl.
CPC ...
H01L 43/02 (2013.01); G11C 11/161 (2013.01); G11C 11/165 (2013.01); G11C 11/18 (2013.01); H01L 43/06 (2013.01); H01L 43/10 (2013.01);
Abstract

An apparatus is provided which comprises one or more magnetoelectric spin orbit (MESO) minority gates with different peripheral complementary metal oxide semiconductor (CMOS) circuit techniques in the device layer including: (1) current mirroring, (2) complementary supply voltages, (3) asymmetrical transistor sizing, and (4) using transmission gates. These MESO minority gates use the multi-phase clock to prevent back propagation of current so that MESO gate can correctly process the input data.


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