The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 12, 2022

Filed:

Jan. 26, 2021
Applicant:

Synopsys. Inc., Mountain View, CA (US);

Inventors:

Dmitry Korchemny, Herzliya, IL;

Nathaniel Azuelos, Modiin, IL;

Boris Gommershtadt, Herzliya, IL;

Alexander Shot, Haifa, IL;

Assignee:

Synopsys, Inc., Mountain View, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 30/3312 (2020.01); G06F 30/34 (2020.01); G06F 119/12 (2020.01);
U.S. Cl.
CPC ...
G06F 30/3312 (2020.01); G06F 30/34 (2020.01); G06F 2119/12 (2020.01);
Abstract

A method of detecting a timing violation between a first sequential element and a second sequential element in a circuit design being emulated in a hardware emulation system includes, in part, determining a timing relationship between first and second clocks applied respectively to the first sequential element and the second sequential element, reconfiguring a combinational logic disposed between the first sequential element and the second sequential element as one or more buffers, setting a delay across the one or more buffers to one or more clock cycles of the hardware emulation system based on the timing relationship, reprogramming the first and second clocks in accordance with the delay, and detecting a timing violation if a change in an output of the first flip-flop is not stored in the second flip-flop within the delay.


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