The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 12, 2022

Filed:

Dec. 26, 2018
Applicant:

Intel Corporation, Santa Clara, CA (US);

Inventors:

Vincent Scarlata, Beaverton, OR (US);

Reshma Lal, Hillsboro, OR (US);

Alpa Narendra Trivedi, Hillsboro, OR (US);

Eric Innis, Hillsboro, OR (US);

Assignee:

INTEL CORPORATION, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H04L 9/32 (2006.01); H04L 9/08 (2006.01); G06F 21/60 (2013.01); G06F 21/76 (2013.01); G06F 12/14 (2006.01); G06F 9/455 (2018.01); G06F 21/57 (2013.01); G06F 21/64 (2013.01); H04L 41/28 (2022.01); G06F 21/79 (2013.01); H04L 41/046 (2022.01); H04L 9/06 (2006.01); G06F 9/38 (2018.01); G06F 12/0802 (2016.01);
U.S. Cl.
CPC ...
G06F 12/1408 (2013.01); G06F 9/3877 (2013.01); G06F 9/45558 (2013.01); G06F 12/0802 (2013.01); G06F 21/57 (2013.01); G06F 21/602 (2013.01); G06F 21/606 (2013.01); G06F 21/64 (2013.01); G06F 21/76 (2013.01); G06F 21/79 (2013.01); H04L 9/0631 (2013.01); H04L 9/0637 (2013.01); H04L 9/083 (2013.01); H04L 9/085 (2013.01); H04L 9/0838 (2013.01); H04L 9/0844 (2013.01); H04L 9/0891 (2013.01); H04L 9/321 (2013.01); H04L 9/3215 (2013.01); H04L 9/3226 (2013.01); H04L 9/3268 (2013.01); H04L 9/3278 (2013.01); H04L 41/046 (2013.01); H04L 41/28 (2013.01); G06F 2009/45591 (2013.01); G06F 2009/45595 (2013.01);
Abstract

Technologies for secure authentication and programming of an accelerator device include a computing device having a processor and an accelerator. The processor establishes a trusted execution environment, which receives a unique device identifier from the accelerator, validates a device certificate for the device identifier, authenticates the accelerator in response to validating the accelerator, validates attestation information of the accelerator, and establishes a secure channel with the accelerator. The trusted execution environment may securely program a data key and a bitstream key to the accelerator, and may encrypt a bitstream image and securely program the bitstream image to the accelerator. The accelerator and a tenant may securely exchange data protected by the data key. The trusted execution environment may be a secure enclave, and the accelerator may be a field programmable gate array (FPGA). Other embodiments are described and claimed.


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