The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jul. 12, 2022
Filed:
Jun. 16, 2020
Applicant:
Intel Corporation, Santa Clara, CA (US);
Inventors:
Sudarshanram Shetty, Portland, OR (US);
Ping Hang Cheung, Folsom, CA (US);
Aravindh Anantaraman, Folsom, CA (US);
Travis Schluessler, Berthoud, CO (US);
Assignee:
Intel Corporation, Santa Clara, CA (US);
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G06F 12/00 (2006.01); G06F 13/00 (2006.01); G06F 13/28 (2006.01); G06F 12/0893 (2016.01); G06F 9/30 (2018.01); G06F 9/50 (2006.01); G06F 11/30 (2006.01); G06F 12/0862 (2016.01); G06F 12/0873 (2016.01);
U.S. Cl.
CPC ...
G06F 12/0893 (2013.01); G06F 9/30043 (2013.01); G06F 9/5016 (2013.01); G06F 11/3037 (2013.01); G06F 12/0862 (2013.01); G06F 12/0873 (2013.01); G06F 2212/1021 (2013.01);
Abstract
An apparatus to facilitate dynamic cache control is disclosed. The apparatus includes one or more processors to profile execution characteristics of a graphics workload at a processing resource to generate profile data indicating a quantity of cache hits that occur at a cache memory and apply one or more cache settings to the cache memory based on the profile data.