The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jul. 12, 2022
Filed:
Oct. 14, 2020
Applicant:
Advantest Corporation, Tokyo, JP;
Inventors:
Olaf Pöppe, Tübingen, DE;
Klaus-Dieter Hilliges, Stuttgart, DE;
Assignee:
Advantest Corporation, Tokyo, JP;
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G01R 31/3183 (2006.01); G01R 31/319 (2006.01); G01R 31/317 (2006.01); G01R 31/3177 (2006.01); G06F 13/20 (2006.01); G06F 11/273 (2006.01);
U.S. Cl.
CPC ...
G01R 31/318307 (2013.01); G01R 31/3177 (2013.01); G01R 31/31712 (2013.01); G01R 31/31713 (2013.01); G01R 31/31724 (2013.01); G01R 31/31905 (2013.01); G01R 31/31907 (2013.01); G01R 31/31908 (2013.01); G01R 31/31926 (2013.01); G06F 11/2733 (2013.01); G06F 13/20 (2013.01);
Abstract
An automated test equipment for testing a device under test comprises an on-chip-system-test controller. The on-chip system test controller comprises at least one debug interface or control interface configured to communicate with the device under test. The on-chip-system-test controller optionally comprises at least one high bandwidth interface configured to communicate with the device under test. The on-chip-system-test controller is configured to control a test of a device-under-test which is a system-on-a chip.