The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 05, 2022

Filed:

Feb. 08, 2021
Applicant:

Samsung Electro-mechanics Co., Ltd., Suwon-si, KR;

Inventors:

Kee Su Jeon, Suwon-si, KR;

Sang Hoon Kim, Suwon-si, KR;

Yong Duk Lee, Suwon-si, KR;

Min Jae Seong, Suwon-si, KR;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H05K 1/02 (2006.01); H05K 1/03 (2006.01); H05K 1/11 (2006.01); H05K 1/18 (2006.01);
U.S. Cl.
CPC ...
H05K 1/0298 (2013.01); H05K 1/0366 (2013.01); H05K 1/0373 (2013.01); H05K 1/111 (2013.01); H05K 1/115 (2013.01); H05K 1/18 (2013.01); H05K 2201/096 (2013.01);
Abstract

A printed circuit board includes: a first insulating layer; a first wiring layer at least partially buried in the first insulating layer; a second insulating layer disposed on an upper surface of the first insulating layer; a second wiring layer at least partially buried in the second insulating layer; and a cavity penetrating through the second insulating layer and a portion of the first insulating layer and exposing a portion of the upper surface of the first insulating layer as a bottom surface of the cavity. The first wiring layer includes a wiring pattern at least partially exposed from the first insulating layer by the cavity, an upper surface of the wiring pattern has a step structure with the upper surface of the first insulating layer exposed by the cavity, and a lower surface of the wiring pattern is coplanar with a lower surface of the first insulating layer.


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