The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 05, 2022

Filed:

Oct. 31, 2019
Applicant:

Kioxia Corporation, Tokyo, JP;

Inventors:

Tsunehiro Ino, Fujisawa, JP;

Yusuke Higashi, Zushi, JP;

Toshinori Numata, Kamakura, JP;

Yuuichi Kamimuta, Yokkaichi, JP;

Assignee:

Kioxia Corporation, Minato-ku, JP;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 29/51 (2006.01); H01L 27/1159 (2017.01); H01L 27/11597 (2017.01); H01L 29/78 (2006.01); H01L 29/49 (2006.01); H01L 27/11587 (2017.01);
U.S. Cl.
CPC ...
H01L 29/516 (2013.01); H01L 27/1159 (2013.01); H01L 27/11597 (2013.01); H01L 29/4983 (2013.01); H01L 29/512 (2013.01); H01L 29/513 (2013.01); H01L 29/517 (2013.01); H01L 29/78391 (2014.09); H01L 27/11587 (2013.01);
Abstract

A semiconductor memory device of an embodiment includes a semiconductor layer; a gate electrode including a first portion, a second portion provided to be spaced apart from the first portion, and a spacer provided between the first portion and the second portion; and a first insulating layer provided between the semiconductor layer and the gate electrode and including a first region containing a ferroelectric, a ferrielectric, or an anti-ferroelectric, a second region containing a ferroelectric, a ferrielectric, or an anti-ferroelectric, and a boundary region provided between the first region and the second region. The first region is positioned between the first portion and the semiconductor layer, the second region is positioned between the second portion and the semiconductor layer, the boundary region is positioned between the spacer and the semiconductor layer, and the boundary region has a chemical composition different from that of the spacer.


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