The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 05, 2022

Filed:

Oct. 30, 2020
Applicant:

Ferroelectric Memory Gmbh, Dresden, DE;

Inventor:

Johannes Ocker, Dresden, DE;

Assignee:
Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H01L 27/11 (2006.01); G11C 11/22 (2006.01); H01L 27/11507 (2017.01); H01L 49/02 (2006.01); H01L 27/11504 (2017.01); H01L 27/11509 (2017.01);
U.S. Cl.
CPC ...
H01L 27/11507 (2013.01); G11C 11/221 (2013.01); G11C 11/2255 (2013.01); G11C 11/2257 (2013.01); G11C 11/2273 (2013.01); G11C 11/2275 (2013.01); H01L 27/11504 (2013.01); H01L 27/11509 (2013.01); H01L 28/55 (2013.01); H01L 28/90 (2013.01);
Abstract

A memory cell arrangement is provided that may include: one or more memory cells, each of the one or more memory cells including: an electrode pillar having a bottom surface and a top surface; a memory material portion surrounding a lateral surface portion of the electrode pillar; an electrode layer surrounding the memory material portion and the lateral surface portion of the electrode pillar, wherein the electrode pillar, the memory material portion, and the electrode layer form a capacitive memory structure; and a field-effect transistor structure comprising a gate structure, wherein the bottom surface of the electrode pillar faces the gate structure and is electrically conductively connected to the gate structure, and wherein the top surface of the electrode pillar faces away from the gate structure.


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