The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 05, 2022

Filed:

Mar. 04, 2020
Applicant:

Yield Microelectronics Corp., Chu-Pei, TW;

Inventors:

Cheng-Ying Wu, Chu-Pei, TW;

Yu-Ting Huang, Chu-Pei, TW;

Wen-Chien Huang, Chu-Pei, TW;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 27/112 (2006.01);
U.S. Cl.
CPC ...
H01L 27/11206 (2013.01);
Abstract

A low-voltage anti-fuse element is provided with a first gate dielectric layer and a first gate sequentially disposed on a substrate. A first ion-doped region is formed in the substrate on one side of the first gate. The first gate includes a body portion and a sharp corner portion extending and gradually reducing from one side of the body portion both adjacent to the first gate dielectric layer. During the operation, the principle of higher density of charges at sharp corners is utilized. When the write voltage is applied between the first gate and the first ion-doped region, a portion of the first gate dielectric layer below the sharp corner portion is liable to break down. Therefore, the breakdown voltage is reduced to achieve the purpose of reducing current consumption, while decreasing the gate area, the element size and production costs.


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