The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 05, 2022

Filed:

Mar. 23, 2021
Applicant:

Micron Technology, Inc., Boise, ID (US);

Inventors:

Yuan He, Boise, ID (US);

Tae H. Kim, Boise, ID (US);

Assignee:

Micron Technology, Inc., Boise, ID (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 7/00 (2006.01); G11C 11/4091 (2006.01); G11C 7/10 (2006.01); H01L 27/06 (2006.01); H01L 27/108 (2006.01);
U.S. Cl.
CPC ...
G11C 11/4091 (2013.01); G11C 7/1012 (2013.01); H01L 27/0688 (2013.01); H01L 27/10805 (2013.01);
Abstract

A memory device can comprise an arrays of memory cells comprising a plurality of vertically stacked tiers of memory cells, a respective plurality of horizontal access lines coupled to each of the plurality of tiers of memory cells, and a plurality of vertical sense lines coupled to each of the plurality of tiers of memory cells. The array of memory cells can further comprise a plurality of multiplexors each coupled to a respective vertical sense line, wherein each of the plurality of multiplexors includes a first portion and a second portion, the first portion is coupled to the array of memory cells and the second portion is formed on a substrate material. The array of memory cells can further comprise a semiconductor under the array (SuA) circuitry comprising a plurality of sense amplifiers, each sense amplifier coupled to a respective subset of the plurality of multiplexors.


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