The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 05, 2022

Filed:

Jan. 26, 2021
Applicant:

Synopsys, Inc., Mountain View, CA (US);

Inventors:

Ruifeng Guo, Portland, OR (US);

Brian Archer, Mountain View, CA (US);

Assignee:

Synopsys, Inc., Mountain View, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 30/398 (2020.01); G06F 30/3308 (2020.01); G06F 30/367 (2020.01); G06F 119/22 (2020.01);
U.S. Cl.
CPC ...
G06F 30/398 (2020.01); G06F 30/3308 (2020.01); G06F 30/367 (2020.01); G06F 2119/22 (2020.01);
Abstract

To specifically identify faults within a semiconductor cell, a SPICE netlist associated with the semiconductor cell design is retrieved, and one or more transistor characteristics are identified within the SPICE netlist. An advanced cell-aware fault model is executed for the semiconductor cell, and results are returned for one or more fault test methods of the advanced cell-aware fault model for a cell of the semiconductor chip design. A method for identifying faults within the semiconductor cell continues by correlating one more faults detected as a result of the fault test methods with one or more transistor characteristics within the SPICE netlist, and a user interface is generated for identifying one or more faulty transistors within the semiconductor chip design.


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