The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jul. 05, 2022
Filed:
Mar. 23, 2020
Applicant:
Intel Corporation, Santa Clara, CA (US);
Inventors:
Ren Wang, Portland, OR (US);
Bin Li, Portland, OR (US);
Andrew J. Herdrich, Hillsboro, OR (US);
Tsung-Yuan C. Tai, Portland, OR (US);
Ramakrishna Huggahalli, Scottsdale, AZ (US);
Assignee:
Intel Corporation, Santa Clara, CA (US);
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 11/30 (2006.01); G06F 11/34 (2006.01); G06F 12/0811 (2016.01); G06F 12/121 (2016.01); G06F 13/16 (2006.01); G06F 13/42 (2006.01); G06F 12/128 (2016.01); G06F 12/084 (2016.01); G06F 12/0888 (2016.01); H04L 67/1097 (2022.01); G06F 13/28 (2006.01);
U.S. Cl.
CPC ...
G06F 11/3466 (2013.01); G06F 11/3037 (2013.01); G06F 11/3089 (2013.01); G06F 11/3409 (2013.01); G06F 12/084 (2013.01); G06F 12/0811 (2013.01); G06F 12/0888 (2013.01); G06F 12/121 (2013.01); G06F 12/128 (2013.01); G06F 13/1668 (2013.01); G06F 13/4282 (2013.01); G06F 13/28 (2013.01); G06F 2201/88 (2013.01); G06F 2201/885 (2013.01); G06F 2212/1016 (2013.01); G06F 2212/1024 (2013.01); G06F 2212/154 (2013.01); G06F 2212/502 (2013.01); G06F 2213/0026 (2013.01); H04L 67/1097 (2013.01);
Abstract
There is disclosed in one example a computing apparatus, including: a processor; a multilevel cache including a plurality of cache levels; a peripheral device configured to write data directly to a selected cache level; and a cache monitoring circuit, including a cache counter to track cache lines evicted from the selected cache level without being processed; and logic to provide a direct write policy according to the cache counter.