The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 05, 2022

Filed:

Dec. 27, 2019
Applicant:

Intel Corporation, Santa Clara, CA (US);

Inventors:

Pratik Marolia, Hillsboro, OR (US);

Rajesh Sankaran, Portland, OR (US);

Assignee:

Intel Corporation, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 16/04 (2006.01); G06F 9/30 (2018.01); G06F 9/38 (2018.01); G06F 12/1027 (2016.01);
U.S. Cl.
CPC ...
G06F 9/30145 (2013.01); G06F 9/3851 (2013.01); G06F 12/1027 (2013.01); G06F 2212/1008 (2013.01);
Abstract

An apparatus and method for hybrid software-hardware coherency. An apparatus comprises one or more processing elements to process data; a memory controller to couple the one or more processing elements to a device memory; an interconnect to couple the one or more processing elements to a host processor memory and to couple a host processor to the device memory; one or more device caches to store cache lines read from the host processor memory and/or the device memory; coherency circuitry to manage an ownership indication for each cache line, the ownership indication to be set to a first value to indicate ownership by the host processor and to be set to a second value to indicate ownership by the processing device, wherein the coherency circuitry is to transfer ownership of a first cache line from the processing device to the host processor by updating the ownership indication from the second value to the first value, the coherency circuitry to provide indirect access to the cache line by the processing device while the ownership indication is set to the first value, the coherency circuitry to maintain the ownership indication at the first value until receiving a request to change the ownership indication.


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