The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 05, 2022

Filed:

Dec. 23, 2019
Applicant:

Intel Corporation, Santa Clara, CA (US);

Inventors:

Yu-Shan Wang, Hillsboro, OR (US);

Martin Clara, Santa Clara, CA (US);

Daniel Gruber, St. Andrae, AT;

Hundo Shin, Santa Clara, CA (US);

Kameran Azadet, San Ramon, CA (US);

Assignee:

Intel Corporation, Santa Clara, CA (US);

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
G06F 1/12 (2006.01); G06F 1/14 (2006.01); G06F 1/08 (2006.01);
U.S. Cl.
CPC ...
G06F 1/12 (2013.01); G06F 1/08 (2013.01); G06F 1/14 (2013.01);
Abstract

An apparatus for generating synchronized clock signals is provided. The apparatus comprises a first circuit comprising a clock divider circuit configured to receive a first clock signal and to generate a second clock signal by frequency dividing the first clock signal. Further, the apparatus comprises a one or more second circuits comprising a respective synchronization circuit configured to receive the first clock signal. The synchronization circuit of one of the one or more second circuits is configured to receive the second clock signal from the first circuit and to resample the second clock signal based on the first clock signal in order to generate a replica of the second clock signal that is in phase with the second clock signal.


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