The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 28, 2022

Filed:

Jul. 22, 2020
Applicant:

Monolithic 3d Inc., San Jose, CA (US);

Inventors:

Zvi Or-Bach, San Jose, CA (US);

Deepak C. Sekar, Sunnyvale, CA (US);

Brian Cronquist, Klamath Falls, OR (US);

Zeev Wurman, Palo Alto, CA (US);

Assignee:

MONOLITHIC 3D INC., Klamath Falls, OR (US);

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H01L 27/06 (2006.01); G03F 9/00 (2006.01); H01L 21/762 (2006.01); H01L 21/84 (2006.01); H01L 23/48 (2006.01); H01L 23/544 (2006.01); H01L 27/02 (2006.01); H01L 27/105 (2006.01); H01L 27/108 (2006.01); H01L 27/11 (2006.01); H01L 27/112 (2006.01); H01L 27/11551 (2017.01); H01L 27/11578 (2017.01); H01L 27/118 (2006.01); H01L 27/12 (2006.01); H01L 29/66 (2006.01); H01L 29/45 (2006.01); H01L 29/786 (2006.01); H01L 27/092 (2006.01); H01L 21/8238 (2006.01); H01L 29/732 (2006.01); H01L 29/808 (2006.01); H01L 21/768 (2006.01); H01L 21/822 (2006.01); H01L 23/367 (2006.01); H01L 23/522 (2006.01); H01L 23/528 (2006.01); H01L 23/532 (2006.01); H01L 23/00 (2006.01); H01L 21/268 (2006.01); H01L 27/088 (2006.01);
U.S. Cl.
CPC ...
H01L 29/732 (2013.01); H01L 21/76898 (2013.01); H01L 21/8221 (2013.01); H01L 23/367 (2013.01); H01L 23/528 (2013.01); H01L 23/5226 (2013.01); H01L 23/53214 (2013.01); H01L 23/53228 (2013.01); H01L 29/66848 (2013.01); H01L 29/808 (2013.01); H01L 21/268 (2013.01); H01L 24/73 (2013.01); H01L 27/088 (2013.01); H01L 29/66545 (2013.01); H01L 2223/5442 (2013.01); H01L 2223/54426 (2013.01); H01L 2223/54453 (2013.01); H01L 2224/16145 (2013.01); H01L 2224/16225 (2013.01); H01L 2224/32145 (2013.01); H01L 2224/32225 (2013.01); H01L 2224/45124 (2013.01); H01L 2224/45147 (2013.01); H01L 2224/48091 (2013.01); H01L 2224/48227 (2013.01); H01L 2224/73204 (2013.01); H01L 2224/73253 (2013.01); H01L 2224/73265 (2013.01); H01L 2924/00011 (2013.01); H01L 2924/10253 (2013.01); H01L 2924/12032 (2013.01); H01L 2924/1301 (2013.01); H01L 2924/1305 (2013.01); H01L 2924/13062 (2013.01); H01L 2924/13091 (2013.01); H01L 2924/14 (2013.01); H01L 2924/15311 (2013.01); H01L 2924/181 (2013.01); H01L 2924/3011 (2013.01); H01L 2924/3025 (2013.01);
Abstract

A method to form a 3D integrated circuit, the method including: providing a first wafer including a first crystalline substrate, a plurality of first transistors, and first copper interconnecting layers, where the first copper interconnecting layers at least interconnect the plurality of first transistors; providing a second wafer including a second crystalline substrate, a plurality of second transistors, and second copper interconnecting layers, where the second copper interconnecting layers at least interconnect the plurality of second transistors; and then performing a face-to-face bonding of the second wafer on top of the first wafer, where the face-to-face bonding includes copper to copper bonding; and thinning the second crystalline substrate to a thickness of less than 5 micro-meters.


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