The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 28, 2022

Filed:

Sep. 11, 2020
Applicants:

Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu, TW;

National Taiwan University, Taipei, TW;

Inventors:

Chung-En Tsai, Hsinchu County, TW;

Fang-Liang Lu, New Taipei, TW;

Pin-Shiang Chen, Taipei, TW;

Chee-Wee Liu, Taipei, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/66 (2006.01); H01L 29/167 (2006.01); H01L 21/223 (2006.01); H01L 21/3065 (2006.01); H01L 29/78 (2006.01); H01L 29/45 (2006.01); H01L 21/3105 (2006.01); H01L 21/02 (2006.01); H01L 29/165 (2006.01); H01L 29/08 (2006.01);
U.S. Cl.
CPC ...
H01L 29/66795 (2013.01); H01L 21/223 (2013.01); H01L 21/3065 (2013.01); H01L 29/167 (2013.01); H01L 29/456 (2013.01); H01L 29/6656 (2013.01); H01L 29/66545 (2013.01); H01L 29/66636 (2013.01); H01L 29/7848 (2013.01); H01L 29/7851 (2013.01); H01L 21/0245 (2013.01); H01L 21/0262 (2013.01); H01L 21/02452 (2013.01); H01L 21/02532 (2013.01); H01L 21/02535 (2013.01); H01L 21/31053 (2013.01); H01L 29/0847 (2013.01); H01L 29/165 (2013.01);
Abstract

A method includes forming a first semiconductor layer over a substrate; forming a second semiconductor layer over the first semiconductor layer; forming a dummy gate structure over the second semiconductor layer; performing an etching process to form a recess in the first and second semiconductor layers; forming a epitaxy structure over in the recess, wherein the epitaxy structure is in contact with the first and second semiconductor layers; performing a solid phase diffusion process to form a doped region in the epitaxy structure, in which the doped region is in contact with the second semiconductor layer and is separated from the first semiconductor layer; and replacing the dummy gate structure with a metal gate structure.


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