The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 28, 2022

Filed:

Nov. 14, 2019
Applicant:

Unimicron Technology Corp., Taoyuan, TW;

Inventors:

Chin-Sheng Wang, Taoyuan, TW;

Ra-Min Tain, Hsinchu County, TW;

Pei-Chang Huang, Taoyuan, TW;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/367 (2006.01); H01L 23/42 (2006.01); H01L 23/498 (2006.01); H01L 23/18 (2006.01); H01L 23/467 (2006.01); H01L 23/14 (2006.01); H01L 21/48 (2006.01); H01L 23/00 (2006.01);
U.S. Cl.
CPC ...
H01L 23/42 (2013.01); H01L 21/4857 (2013.01); H01L 23/14 (2013.01); H01L 23/18 (2013.01); H01L 23/3672 (2013.01); H01L 23/467 (2013.01); H01L 23/49822 (2013.01); H01L 23/49838 (2013.01); H01L 24/48 (2013.01); H01L 2224/48228 (2013.01);
Abstract

A package substrate includes a multilayer circuit structure, a gas-permeable structure, a heat conducting component, a first circuit layer, a second circuit layer and a build-up circuit structure. The gas-permeable structure and the heat conducting component are respectively disposed in a first and a second through holes of the multilayer circuit structure. The first and the second circuit layers are respectively disposed on an upper and a lower surfaces of the multilayer circuit structure and expose a first and a second sides of the gas-permeable structure. The build-up circuit structure is disposed on the first circuit layer and includes at least one patterned photo-imageable dielectric layer and at least one patterned circuit layer alternately stacked. The patterned circuit layer is electrically connected to the first circuit layer by at least one opening. The build-up circuit structure and the first circuit layer exposed by a receiving opening form a recess.


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