The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 28, 2022

Filed:

Jun. 25, 2020
Applicant:

Micron Technology, Inc., Boise, ID (US);

Inventors:

Zer Liang, Tokyo, JP;

Minari Arai, Saitama, JP;

Takuya Nakanishi, Ibaraki, JP;

Assignee:

Micron Technology, Inc., Boise, ID (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 29/42 (2006.01); G11C 29/44 (2006.01); G11C 29/14 (2006.01); G11C 29/12 (2006.01); G11C 7/22 (2006.01); G11C 7/06 (2006.01);
U.S. Cl.
CPC ...
G11C 29/42 (2013.01); G11C 7/065 (2013.01); G11C 7/222 (2013.01); G11C 29/1201 (2013.01); G11C 29/14 (2013.01); G11C 29/44 (2013.01);
Abstract

Error correction control (ECC) circuits for memory devices and related apparatuses, systems, and methods are disclosed. An apparatus includes an ECC control circuit input configured to receive read data from a plurality of memory banks of a memory cell array via a single set of shared main input/output (MIO) lines. The single set of shared MIO lines are shared by the plurality of memory banks. The apparatus also includes a single ECC control circuit configured to generate corrected read data responsive to the read data received by the ECC control circuit input. The apparatus further includes an ECC control circuit output configured to provide the corrected read data generated by the single ECC control circuit to a global data bus.


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