The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 28, 2022

Filed:

Feb. 19, 2021
Applicant:

Nif/t, Llc, Los Gatos, CA (US);

Inventors:

Mammen Thomas, Hercules, CA (US);

Robert J. Strain, San Jose, CA (US);

Assignee:

NIF/T, LLC, Reno, NV (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 11/24 (2006.01); G11C 11/402 (2006.01); G11C 11/4074 (2006.01); H01L 27/092 (2006.01); H01L 27/108 (2006.01); G11C 11/4097 (2006.01);
U.S. Cl.
CPC ...
G11C 11/4023 (2013.01); G11C 11/4074 (2013.01); G11C 11/4097 (2013.01); H01L 27/0924 (2013.01); H01L 27/10829 (2013.01);
Abstract

A flat field transistor (FFT) based dynamic random-access memory (DRAM) (FFT-DRAM) is disclosed. The FFT-DRAM comprises an epitaxially grown source region comprising a source extension and an epitaxial source over and in contact with the source extension. The epitaxially grown source region is over a surface of a semiconductor substrate. The FFT-DRAM further comprises a trench capacitor structurally integrated into the epitaxially grown source region. The trench capacitor has a first terminal formed by the epitaxially grown source region and a second terminal being a conductive material filling one or more trenches of the trench capacitor. The second terminal is connected to a ground terminal or a fixed voltage terminal.


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