The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 21, 2022

Filed:

Dec. 04, 2020
Applicant:

Globalfoundries U.s. Inc., Santa Clara, CA (US);

Inventors:

Dzung T. Tran, Austin, TX (US);

Shibly S. Ahmed, San Jose, CA (US);

Assignee:

GlobalFoundries U.S. Inc., Santa Clara, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H03K 19/0175 (2006.01); H03K 19/0185 (2006.01); H03K 19/20 (2006.01); H03K 19/003 (2006.01);
U.S. Cl.
CPC ...
H03K 19/018521 (2013.01); H03K 19/003 (2013.01); H03K 19/0175 (2013.01); H03K 19/20 (2013.01);
Abstract

Embodiments of the disclosure provide an input output (IO) structure in which complimentary nodes of a level shifter are utilized to logically block the output of the IO structure from switching until both power supplies to the IO structure are powered up. An illustrative level shifter includes: a cross-coupled pair of PFETs configured to output complimentary voltage values at a first node and a second node; a control circuit configured to select which of the complementary voltage values are output to the first node and second node; a logic inverter having an input coupled to the first node and an output coupled to a third node; and a NAND gate having inputs coupled to the second node and third node and that generates a level shifted output.


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