The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 21, 2022

Filed:

Nov. 12, 2019
Applicant:

Winbond Electronics Corp., Taichung, TW;

Inventors:

Hao-Chuan Chang, Taichung, TW;

Kai Jen, Taichung, TW;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/778 (2006.01); H01L 29/20 (2006.01); H01L 29/205 (2006.01); H01L 29/423 (2006.01); H01L 27/108 (2006.01); H01L 21/285 (2006.01); H01L 29/66 (2006.01);
U.S. Cl.
CPC ...
H01L 29/7789 (2013.01); H01L 21/28581 (2013.01); H01L 27/10823 (2013.01); H01L 27/10876 (2013.01); H01L 29/2003 (2013.01); H01L 29/205 (2013.01); H01L 29/42316 (2013.01); H01L 29/66462 (2013.01); H01L 29/7786 (2013.01);
Abstract

A semiconductor device and a manufacturing method thereof are provided. The semiconductor device includes a substrate, a first channel layer, a first barrier layer, a gate electrode and an insulating structure. The substrate has a recess, and the first channel layer, the first barrier layer, the gate electrode and the insulating structure are disposed in the recess. The first channel layer covers a surface of the recess. The first barrier layer is disposed on a surface of the first channel layer. A surface of a bottom portion of the first barrier layer is covered by the gate electrode, and a top surface of the gate electrode is lower than a topmost surface of the substrate. Surfaces of the gate electrode and a top portion of the first barrier layer are covered by the insulating structure.


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