The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 21, 2022

Filed:

Mar. 31, 2020
Applicant:

Southeast University, Jiangsu, CN;

Inventors:

Jing Zhu, Jiangsu, CN;

Ankang Li, Jiangsu, CN;

Long Zhang, Jiangsu, CN;

Weifeng Sun, Jiangsu, CN;

Shengli Lu, Jiangsu, CN;

Longxing Shi, Jiangsu, CN;

Assignee:

SOUTHEAST UNIVERSITY, Jiangsu, CN;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/73 (2006.01); H01L 29/739 (2006.01); H01L 29/10 (2006.01);
U.S. Cl.
CPC ...
H01L 29/7394 (2013.01); H01L 29/1095 (2013.01);
Abstract

A lateral insulated gate bipolar transistor (IGBT) with a low turn-on overshoot current is provided to reduce a peak value of a current flowing through a device during turn-on of a second gate pulse while preventing a current capability and a withstand voltage capability from being degraded. The lateral IGBT includes: a buried oxygen arranged on a P-type substrate, an N-type drift region arranged on the buried oxygen, on which a P-type body region and an N-type buffer region are arranged, a P-type collector region arranged in the N-type buffer region, a field oxide layer arranged above the N-type drift region, a P-type well region arranged in the P-type body region, and a P-type emitter region and an emitter region arranged in the P-type well region, where inner boundaries of the foregoing 4 regions are synchronously recessed to form a pinch-off region. A gate oxide layer is arranged on a surface of the P-type body region, and a polysilicon gate is arranged on the gate oxide layer. The polysilicon gate includes a first gate located above the surface of the P-type body region and a second gate located above the pinch-off region and the N-type drift region. The first gate is connected to a first gate resistor, and the second gate is connected to a second gate resistor.


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