The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 21, 2022

Filed:

Aug. 13, 2020
Applicant:

Synopsys, Inc., Mountain View, CA (US);

Inventors:

Sankaranarayanan Srinivasan, San Jose, CA (US);

Senthilkumar Thoravi Rajavel, Hillsboro, OR (US);

Vinod Kumar Nakkala, Sunnyvale, CA (US);

Avinash Anantharamu, Sunnyvale, CA (US);

Pierre Clement, Antony, FR;

Saibal Ghosh, Sunnyvale, CA (US);

Sashikala Oblisetty, Cupertino, CA (US);

Etienne Lepercq, Shrewsbury, MA (US);

Assignee:

Synopsys, Inc., Mountain View, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 30/27 (2020.01); G06F 30/3323 (2020.01); G06F 119/12 (2020.01);
U.S. Cl.
CPC ...
G06F 30/27 (2020.01); G06F 30/3323 (2020.01); G06F 2119/12 (2020.01);
Abstract

A method includes generating a netlist for a circuit design and predicting, by applying a first machine learning model to the netlist, a first compile time for the circuit design. The method also includes predicting, by applying a second machine learning model to the netlist, a first place and route strategy based on the first compile time. The method further includes adjusting a logic of the circuit design in accordance with the first place and route strategy.


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