The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 21, 2022

Filed:

May. 31, 2019
Applicant:

Nxp Usa, Inc., Austin, TX (US);

Inventors:

Michael Rohleder, Unterschleissheim, DE;

George Adrian Ciusleanu, Marasesti, RO;

David Allen Brown, Austin, TX (US);

Marcus Mueller, Munich, DE;

Assignee:

NXP USA, Inc., Austin, TX (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 9/46 (2006.01); G06F 9/48 (2006.01); G06F 13/40 (2006.01); G06F 13/16 (2006.01); G06F 9/54 (2006.01);
U.S. Cl.
CPC ...
G06F 9/4881 (2013.01); G06F 9/542 (2013.01); G06F 13/1668 (2013.01); G06F 13/4027 (2013.01);
Abstract

A processor scheduling structure, a method and an integrated circuit are provided. In accordance with at least one embodiment, the processor scheduling structure comprises a processor circuit and an operating system task aware caching (OTC) controller circuit coupled to the processor circuit. The OTC controller circuit comprises a load request timer, a load sequence queue (LSQ), and a request arbiter. The timer and the LSQ are coupled to and provide inputs to the request arbiter. The processor circuit comprises an internal memory and a processor core. The OTC controller circuit is configured to schedule processor tasks for the processor circuit in accordance with both priority-based scheduling, using the LSQ, and time-triggered scheduling, using the load request timer.


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