The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jun. 14, 2022
Filed:
Sep. 24, 2021
Cypress Semiconductor Corporation, San Jose, CA (US);
Kazuyoshi Futamura, Nagoya, JP;
Kazuhiro Tomita, Kasugai, JP;
Koji Okada, Yokohama, JP;
Hiroyuki Matsunami, Tajimi, JP;
Cypress Semiconductor Corporation, San Jose, CA (US);
Abstract
A device includes a master delay-lock loop (DLL) having a phase frequency detector connected in series with a charge pump that is to generate a control voltage. A slave DLL is coupled to the master DLL and has a delay line including a buffer to receive a slave clock and a series of delay cells coupled between the buffer and an output terminal that is to output a delay clock, the series of delay cells variably controlled by the control voltage. The master DLL and the slave DLL are powered by a power supply that experiences undershoot or overshoot in response to a load transient. A dummy load is coupled between the delay line of the slave DLL and an output of the power supply, the dummy load including an exclusive OR gate that receives, as inputs, a first output of the buffer and the delay clock.