The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 14, 2022

Filed:

Feb. 18, 2020
Applicant:

Industrial Technology Research Institute, Hsinchu, TW;

Inventors:

Te-Hsun Lin, Hsinchu, TW;

Chen-Tsai Yang, Taoyuan, TW;

Kuan-Chu Wu, Kaohsiung, TW;

Shao-An Yan, New Taipei, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/00 (2006.01); H01L 23/538 (2006.01); H01L 23/31 (2006.01); H01L 23/14 (2006.01); H01L 23/498 (2006.01);
U.S. Cl.
CPC ...
H01L 23/562 (2013.01); H01L 23/145 (2013.01); H01L 23/3121 (2013.01); H01L 23/49838 (2013.01); H01L 23/5386 (2013.01);
Abstract

A chip package structure including a substrate, a redistribution layer (RDL), a chip and an encapsulant is provided. The RDL is disposed on the substrate. The chip is disposed on the RDL and is electrically connected with the RDL. The encapsulant is disposed on the RDL and encapsulates the chip. The chip is located in the high stress region. From a top view, the chip is located in the high stress region, and the low stress region surrounds the high stress region. The RDL includes at least one first device located in the high stress region. From the top view, the extending direction of the at least one first device is parallel to a stress direction at a position thereof.


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