The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 14, 2022

Filed:

Dec. 08, 2020
Applicant:

Taiwan Semiconductor Manufacturing Company Ltd., Hsinchu, TW;

Inventors:

Tai-Yi Chen, Hsinchu, TW;

Yung-Chow Peng, Hsinchu, TW;

Chung-Chieh Yang, Hsinchu County, TW;

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/522 (2006.01); H03M 1/38 (2006.01); H01L 23/552 (2006.01); H01L 49/02 (2006.01);
U.S. Cl.
CPC ...
H01L 23/5225 (2013.01); H01L 23/5223 (2013.01); H01L 23/5226 (2013.01); H01L 23/552 (2013.01); H01L 28/40 (2013.01); H01L 28/60 (2013.01); H01L 28/86 (2013.01); H01L 28/92 (2013.01); H03M 1/38 (2013.01);
Abstract

An integrated circuit structure includes a first conductive plate, a second conductive plate, a plurality of conductive lines, and a plurality of conductive vias. The first conductive plate is disposed in a first layer on a semiconductor substrate. The second conductive plate is disposed in a second layer on the semiconductor substrate. The plurality of conductive lines are disposed in the first layer for surrounding the first conductive plate. The plurality of conductive vias are arranged to couple the plurality of conductive lines to the second conductive plate. The second layer is different from the first layer, and the first conductive plate is physically separated from the second conductive plate, the plurality of conductive lines, and the plurality of conductive vias.


Find Patent Forward Citations

Loading…