The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 14, 2022

Filed:

Oct. 29, 2020
Applicants:

Stmicroelectronics International N.v., Geneva, CH;

Stmicroelectronics Application Gmbh, Aschheim-Dornach, DE;

Stmicroelectronics S.r.l., Agrate Brianza, IT;

Inventors:

Avneep Kumar Goyal, Greater Noida, IN;

Deepak Baranwal, Greater Noida, IN;

Thomas Szurmant, Munich, DE;

Nicolas Bernard Grossier, Oreno di Vimercate, IT;

Assignees:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G01R 31/317 (2006.01); G01R 31/3185 (2006.01); G01R 31/3193 (2006.01); G06F 11/34 (2006.01); G01R 31/319 (2006.01); G06F 11/36 (2006.01);
U.S. Cl.
CPC ...
G01R 31/31727 (2013.01); G01R 31/31713 (2013.01); G01R 31/31723 (2013.01); G01R 31/31725 (2013.01); G01R 31/31922 (2013.01); G01R 31/31937 (2013.01); G01R 31/318525 (2013.01); G06F 11/34 (2013.01); G06F 11/348 (2013.01); G06F 11/36 (2013.01);
Abstract

A testing tool includes a clock generation circuit generating a test clock and outputting the test clock via a test clock output pad, data processing circuitry clocked by the test clock, and data output circuitry receiving data output from the data processing circuitry and outputting the data via an input/output (IO) pad, the data output circuitry being clocked by the test clock. The testing tool also includes a programmable delay circuit generating a delayed version of the test clock, and data input circuitry receiving data input via the IO pad, the data input circuitry clocked by the delayed version of the test clock. The delayed version of the test clock is delayed to compensate for delay between transmission of a pulse of the test clock via the test clock output pad to an external computer and receipt of the data input from the external computer via the IO pad.


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