The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 07, 2022

Filed:

Mar. 26, 2021
Applicant:

Intel Corporation, Santa Clara, CA (US);

Inventors:

Hsinho Wu, Santa Clara, CA (US);

Masashi Shimanouchi, San Jose, CA (US);

Peng Li, Palo Alto, CA (US);

Assignee:

Intel Corporation, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H04J 14/02 (2006.01); H04L 25/03 (2006.01); H04L 25/14 (2006.01); G06N 20/00 (2019.01); H03H 21/00 (2006.01);
U.S. Cl.
CPC ...
H04L 25/03019 (2013.01); H04L 25/03114 (2013.01); H04L 25/03343 (2013.01); H04L 25/03878 (2013.01); H04L 25/14 (2013.01); G06N 20/00 (2019.01); H03H 21/0012 (2013.01); H04J 14/02 (2013.01); H04L 2025/03802 (2013.01);
Abstract

Systems and methods for electronic devices including two or more semiconductor devices coupled via an interconnect. The interconnect includes multiple lanes each having a link between the first and second semiconductor devices. One or more lanes of the multiple lanes each include clock and data recovery circuitry to perform full clock and data recovery. One or more other lanes of the multiple lanes each do not include clock and data recovery circuitry and instead includes a phase adjustment and clock multiplier circuit that is slave to clock and data recovery circuitry of the one or more lanes.


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