The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 07, 2022

Filed:

Apr. 10, 2019
Applicant:

Atomera Incorporated, Los Gatos, CA (US);

Inventor:

Robert John Stephenson, Duxford, GB;

Assignee:

ATOMERA INCORPORATED, Los Gatos, CA (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G02B 6/12 (2006.01); H01L 27/12 (2006.01); H01L 29/15 (2006.01); G02F 1/017 (2006.01); H01L 33/06 (2010.01); H01L 23/522 (2006.01); G02B 6/134 (2006.01); H01L 27/15 (2006.01); H01L 33/00 (2010.01); H01L 33/34 (2010.01); H01L 33/58 (2010.01); H01L 21/02 (2006.01); H01L 31/0352 (2006.01); H01L 33/04 (2010.01);
U.S. Cl.
CPC ...
H01L 33/06 (2013.01); G02B 6/12004 (2013.01); G02B 6/134 (2013.01); G02F 1/01708 (2013.01); H01L 21/02507 (2013.01); H01L 23/5226 (2013.01); H01L 27/1207 (2013.01); H01L 27/15 (2013.01); H01L 29/152 (2013.01); H01L 33/0054 (2013.01); H01L 33/34 (2013.01); H01L 33/58 (2013.01); G02B 6/12 (2013.01); G02B 2006/12061 (2013.01); G02B 2006/12142 (2013.01); G02F 1/01766 (2021.01); H01L 31/035236 (2013.01); H01L 33/04 (2013.01); H01L 2933/0058 (2013.01);
Abstract

A method for making a semiconductor device may include forming a plurality of waveguides on a substrate, and forming a superlattice overlying the substrate and waveguides. The superlattice may include a plurality of stacked groups of layers, with each group of layers comprising a plurality of stacked base semiconductor monolayers defining a base semiconductor portion, and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions. The method may further include forming an active device layer on the superlattice comprising at least one active semiconductor device.


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