The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jun. 07, 2022
Filed:
Jul. 22, 2020
Taiwan Semiconductor Manufacturing Company Ltd., Hsinchu, TW;
Tsmc China Company, Limited, Shanghai, CN;
TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., Hsinchu, TW;
TSMC CHINA COMPANY, LIMIIED, Shanghai, CN;
Abstract
An integrated circuit includes a bias pad within a buried oxide layer. A layer of semiconductor material is over the buried oxide layer. The layer of semiconductor material includes a doped regions for a transistor. An inter layer dielectric (ILD) material covers the layer of semiconductor material and a gate electrode for the transistor. The integrated circuit includes one or more bias contacts extending through the ILD material within an isolation region in the layer of semiconductor material. Bias contacts electrically connect to the first bias pad. The isolation structure insulates the one or more bias contacts from the doped regions of the transistor within the layer of semiconductor material. The one or more bias contacts are electrically connected to an interconnection structure of the integrated circuit which is configured to connect a voltage source to the bias pad.