The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 07, 2022

Filed:

Nov. 20, 2020
Applicant:

Samsung Electronics Co., Ltd., Suwon-si, KR;

Inventors:

Jong-youn Kim, Seoul, KR;

Seok-hyun Lee, Hwaseong-si, KR;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/538 (2006.01); H01L 21/48 (2006.01); H01L 21/56 (2006.01); H01L 21/683 (2006.01); H01L 23/367 (2006.01); H01L 23/00 (2006.01); H01L 25/065 (2006.01); H01L 25/18 (2006.01);
U.S. Cl.
CPC ...
H01L 23/5385 (2013.01); H01L 21/486 (2013.01); H01L 21/4853 (2013.01); H01L 21/4857 (2013.01); H01L 21/565 (2013.01); H01L 21/568 (2013.01); H01L 21/6835 (2013.01); H01L 23/3675 (2013.01); H01L 23/5384 (2013.01); H01L 23/5386 (2013.01); H01L 24/16 (2013.01); H01L 24/81 (2013.01); H01L 25/0655 (2013.01); H01L 24/32 (2013.01); H01L 24/73 (2013.01); H01L 25/18 (2013.01); H01L 2221/68345 (2013.01); H01L 2221/68359 (2013.01); H01L 2224/16227 (2013.01); H01L 2224/32225 (2013.01); H01L 2224/73204 (2013.01); H01L 2224/81005 (2013.01);
Abstract

Provided is a semiconductor package including an interposer. The semiconductor package includes: a package base substrate; a lower redistribution line structure disposed on the package base substrate and including a plurality of lower redistribution line patterns; at least one interposer including a plurality of first connection pillars spaced apart from each other on the lower redistribution line structure and connected respectively to portions of the plurality of lower redistribution line patterns, and a plurality of connection wiring patterns; an upper redistribution line structure including a plurality of upper redistribution line patterns connected respectively to the plurality of first connection pillars and the plurality of connection wiring patterns, on the plurality of first connection pillars and the at least one interposer; and at least two semiconductor chips adhered on the upper redistribution line structure while being spaced apart from each other.


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