The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 07, 2022

Filed:

Jun. 30, 2020
Applicant:

Sandisk Technologies Llc, Addison, TX (US);

Inventors:

Yu-Chung Lien, San Jose, CA (US);

Fanglin Zhang, Fremont, CA (US);

Zhuojie Li, Santa Clara, CA (US);

Huai-Yuan Tseng, San Ramon, CA (US);

Assignee:

SanDisk Technologies LLC, Addison, TX (US);

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
G11C 16/06 (2006.01); G11C 16/34 (2006.01); G11C 16/04 (2006.01); G11C 16/10 (2006.01); H01L 27/11582 (2017.01); G11C 16/26 (2006.01); H01L 27/11565 (2017.01); G11C 11/56 (2006.01);
U.S. Cl.
CPC ...
G11C 16/3459 (2013.01); G11C 16/0483 (2013.01); G11C 16/10 (2013.01); G11C 11/5671 (2013.01); G11C 16/26 (2013.01); H01L 27/11565 (2013.01); H01L 27/11582 (2013.01);
Abstract

Apparatus and methods are described to program memory cells and verify stored values programmed into the cells. The next stage in stored memory can be moved to the current verification iteration when certain conditions are met. Verification can include counting bits that exceed a voltage value for a stage being verified to produce a bit count number and determining if the bit count number for the stage being verified meets a threshold value. If the bit count number does not meet the threshold, the verification process can continue with a current verify iteration and thereafter move to a next verify iteration. If the bit count number does meet the threshold, the process can add a next stage to the current verify iteration and thereafter move to a next verify iteration.


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