Systems and methods for accurate voltage impact on integrated timing simulation

Abstract

Systems and methods are provided for simulating an integrated circuit system. A file representative of an integrated circuit layout is received, the integrated circuit layout including a plurality of cells and characteristics of power supply and ground paths to each cell. A vulnerable cell of the integrated circuit layout based on a vulnerability characteristic of the vulnerable cell. A power analysis of a portion of the integrated circuit layout is performed to determine a plurality of power and ground levels within a timing window for each of a plurality of cells including the vulnerable cell. A timing analysis of the vulnerable cell is performed, where the timing analysis receives a single power level and single ground level for the vulnerable cell and determines a slack level for the vulnerable cell. An at risk path is identified based on the vulnerable cell slack level, and a dynamic power/ground simulation of one or more cells in the at risk path is performed.