The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 07, 2022

Filed:

Sep. 01, 2020
Applicant:

Nxp Usa, Inc., Austin, TX (US);

Inventors:

Ankur Behl, New Delhi, IN;

Vikas Agarwal, Agra, IN;

Assignee:

NXP USA, INC., Austin, TX (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 9/52 (2006.01); G06F 9/50 (2006.01); G06F 13/40 (2006.01); G06F 9/30 (2018.01);
U.S. Cl.
CPC ...
G06F 9/52 (2013.01); G06F 9/30098 (2013.01); G06F 9/5038 (2013.01); G06F 9/5061 (2013.01); G06F 13/4004 (2013.01); G06F 2213/0038 (2013.01);
Abstract

A centralized access control circuit includes a memory, a sub-circuit, and a memory controller. The memory includes a plurality of lock bits mapped to a plurality of bytes of a peripheral register included in a peripheral. The sub-circuit receives, from a processor core, an access request to access a set of bytes of the plurality of bytes. The sub-circuit grants a first level of access privilege to the processor core based on an identifier of the processor core and an address of the set of bytes included in the access request. The memory controller receives the access request and grants, based on a value of each of a set of lock bits mapped to the set of bytes, a second level of access privilege to the processor core. The processor core accesses the set of bytes based on the first and second levels of access privileges.


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