Pre-memory initialization multithread parallel computing platform

Abstract

A computing device that implements a multithread parallel processing computing platform prior to initialization of system memory is provided. To implement this platform, the computing device executes enhanced firmware that defines a plurality of application processors (APs) under the control of a boot-strap processor (BSP). The BSP preserves backward compatibility of the APs by configuring cross-reference circuitry (e.g., a programmable attribute map) to reroute memory access requests generated by the APs that are addressed to a wakeup buffer to a redirected memory address. Memory at the redirected memory address stores AP initialization instructions and instructions to retrieve and process early stage process instructions stored elsewhere (e.g., in fast access cache memory). The APs, in parallel, execute the initialization instructions and the early stage process instructions stored in cache to complete an early stage process, such as memory training.