The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jun. 07, 2022
Filed:
Jul. 13, 2020
Applicant:
Intel Corporation, Santa Clara, CA (US);
Inventors:
Harshad S. Sane, Portland, OR (US);
Anup Mohan, Milpitas, CA (US);
Kshitij A. Doshi, Tempe, AZ (US);
Mark A. Schmisseur, Phoenix, AZ (US);
Assignee:
INTEL CORPORATION, Santa Clara, CA (US);
Primary Examiner:
Int. Cl.
CPC ...
G06F 9/30 (2018.01); G06F 12/0808 (2016.01); G06F 9/38 (2018.01); G06F 12/126 (2016.01); G06F 12/0888 (2016.01); G06F 12/0862 (2016.01);
U.S. Cl.
CPC ...
G06F 9/30047 (2013.01); G06F 9/3009 (2013.01); G06F 9/30043 (2013.01); G06F 9/3826 (2013.01); G06F 12/0808 (2013.01); G06F 12/0862 (2013.01); G06F 12/0888 (2013.01); G06F 12/126 (2013.01);
Abstract
A computing system includes a memory controller having a plurality of bypass parameters set by a software program, a thresholds matrix to store threshold values selectable by the plurality of bypass parameters, and a bypass function to determine whether a first cache line is to be displaced with a second cache line in a first memory or the first cache line remains in the first memory and the second cache line is to be accessed by at least one of a processor core and the cache from a second memory.