The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 07, 2022

Filed:

Aug. 05, 2020
Applicant:

Micron Technology, Inc., Boise, ID (US);

Inventors:

Kalyan Chakravarthy C. Kavalipurapu, Hyderabad, IN;

Chang H. Siau, Saratoga, CA (US);

Shigekazu Yamada, Tokyo, JP;

Assignee:

MICRON TECHNOLOGY, INC., Boise, ID (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 3/00 (2006.01); G06F 3/06 (2006.01); G11C 16/10 (2006.01); G11C 16/14 (2006.01); G11C 16/08 (2006.01); G11C 16/26 (2006.01); G11C 16/04 (2006.01);
U.S. Cl.
CPC ...
G06F 3/0659 (2013.01); G06F 3/0604 (2013.01); G06F 3/0683 (2013.01); G11C 16/08 (2013.01); G11C 16/10 (2013.01); G11C 16/14 (2013.01); G11C 16/26 (2013.01); G11C 16/0483 (2013.01);
Abstract

A memory device includes a memory array comprising a plurality of planes, a primary plane driver circuit comprising components to support read operations, program operations, and erase operations on any of the plurality of planes, and a secondary plane driver circuit comprising components to support read operations on an associated one of the plurality of planes. The primary plane driver circuit is configured to perform a first read operation on a first plane of the plurality of planes and the secondary plane driver circuit is configured to perform a second read operation on a second plane of the plurality of planes concurrently with the first read operation.


Find Patent Forward Citations

Loading…