The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
May. 31, 2022
Filed:
Sep. 24, 2019
Board of Regents of the University of Nebraska, Lincoln, NE (US);
Nishtha Sharma Gaul, Richardson, TX (US);
Andrew Marshall, Dallas, TX (US);
Peter A. Dowben, Crete, NE (US);
Dmitri E. Nikonov, Beaverton, OR (US);
BOARD OF REGENTS, THE UNIVERSITY OF TEXAS SYSTEM, Austin, TX (US);
BOARD OF REGENTS OF THE UNIVERSITY OF NEBRASKA, Lincoln, NE (US);
INTEL CORPORATION, Santa Clara, CA (US);
Abstract
Logic circuits constructed with magnetoelectric (ME) transistors are described herein. A ME logic gate device can include at least one conducting device, for example, at least one MOS transistor; and at least one ME transistor coupled to the at least one conducting device. The ME transistor can be a ME field effect transistor (ME-FET), which can be can be an anti-ferromagnetic spin-orbit read (AFSOR) device or a non-AFSOR device. The gates and logic circuits described herein can be included as standard cells in a design library. Cells of the cell library can include standard cells for a ME inverter device, a ME minority gate device, a ME majority gate device, a ME full adder, a ME XNOR device, a ME XOR device, or a combination thereof.